Cascode Amplifier: Analysis and Design

The Cascode Amplifier

The cascode is one of the most important compound topologies in analog design. It stacks a common-gate (or common-base) transistor on top of a common-source (or common-emitter) transistor, and in doing so it solves two problems that limit a single gain stage at once: it multiplies the output resistance up to $g_m r_o^2$, and it nearly eliminates the Miller multiplication of the input capacitance, sharply widening the bandwidth. The two devices share the same bias current, so the cascode costs almost no extra power. This tutorial walks through the small-signal analysis step by step, derives the output resistance and gain, explains the Miller benefit, and finishes with a worked example. Familiarity with the MOSFET and BJT small-signal models is assumed.

The Topology

In a MOS cascode, transistor $M_1$ is the input common-source device: the signal drives its gate, its source is at AC ground. Transistor $M_2$ sits on top, its source connected to the drain of $M_1$, its gate held at a fixed DC bias (AC ground), and the output taken at its drain. Because $M_2$ is configured common-gate, it passes the current from $M_1$ straight through while presenting a very low impedance at its source and a very high impedance at its drain. That impedance transformation is the entire point.

Step-by-Step: Output Resistance

To find $R_{out}$, set the input to zero and push a test current $i_x$ into the output node, measuring the resulting voltage $v_x$. With $v_i = 0$, device $M_1$ is off as a driver and simply presents its output resistance $r_{o1}$ at the source of $M_2$. The classic result for the resistance looking into the drain of a common-gate device with a source degeneration $R_S$ is

Here the degeneration is the output resistance of the bottom device, $R_S = r_{o1} \approx r_{o2} = r_o$. Substituting:

The cascode has boosted the output resistance by the intrinsic gain $g_m r_o$ compared with a single device's $r_o$. (For a BJT cascode the ceiling is softened by the finite $r_\pi$; the resistance looking into the collector saturates at roughly $\beta r_o$rather than growing without bound, but the boost over a single stage is still enormous.)

Step-by-Step: Voltage Gain

Driving the cascode with an ideal current-source load (so the load resistance is at least as large as $R_{out}$), the gain is the input transconductance times the output resistance:

A single common-source stage maxes out at an intrinsic gain of $g_m r_o$; the cascode squares it. With a resistive load $R_L$ instead, the gain reverts to $A_v \approx -g_{m1}(R_L \parallel R_{out})$, which simply becomes $-g_{m1} R_L$ when $R_L \ll R_{out}$ — so the cascode only pays off when paired with a high-impedance (active) load.

Bandwidth: Killing the Miller Effect

In a plain common-source stage, the gate-to-drain capacitance $C_{gd}$ is multiplied by the Miller factor $(1 + |A_v|)$, because the drain swings hard in the opposite direction to the gate. This Miller capacitance dominates the input pole and chokes the bandwidth. In the cascode, the drain of $M_1$ connects to the low-impedance source of $M_2$, so the voltage gain from $M_1$'s gate to its drain is only about $-g_{m1}/g_{m2} \approx -1$. The Miller multiplier on $C_{gd1}$ collapses from $(1 + |A_v|)$ to roughly 2:

The huge gain that used to multiply $C_{gd1}$ now appears at $M_2$'s drain, where it acts on the output node, not the input — so it does not slow the input pole. The result is a stage with both high gain and wide bandwidth, breaking the usual gain-bandwidth tradeoff of a single transistor.

Why the Impedance Boost Happens Physically

The mathematics of $g_m r_o^2$ can feel like an accident of algebra, so it is worth seeing the mechanism. Imagine wiggling the output voltage at the drain of the top transistor. That wiggle would ordinarily push current back through the device, but the common-gate transistor's own feedback resists it: a rise in its source voltage (caused by current flowing down into $r_{o1}$) reduces its $v_{gs}$, which throttles the current it will pass. The transistor actively fights any current that the output disturbance tries to inject. The strength of that pushback is the loop gain $g_{m2} r_{o2}$, and it multiplies the bottom device's resistance up to the cascode value. This is local series feedback, the same mechanism as emitter or source degeneration, applied here to raise output resistance rather than to stabilize gain.

Seen this way, the cascode is not a special trick but a particularly clean application of a general principle: degenerating a transistor with a resistance $R_S$ raises the resistance looking into its output by roughly the factor $g_m R_S$. The cascode just chooses $R_S$ to be another transistor's $r_o$, which is the largest convenient resistance available, and so achieves the largest convenient boost. The same insight tells you immediately why a triple cascode raises the resistance again by another factor of $g_m r_o$, at the cost of yet more voltage headroom — each stacked device needs its own slice of the supply to stay in saturation, which is the practical limit on how high you can stack.

The bandwidth benefit follows the same logic from the opposite direction. The reason a plain common-source stage is slow is that its large inverting gain magnifies the input capacitance through the Miller effect. By terminating the input device into a low impedance instead of a high-gain node, the cascode denies the Miller effect the large voltage swing it needs to multiply $C_{gd}$. The gain has not disappeared; it has merely been relocated to the output node, where it can do its job without poisoning the input pole. Understanding this relocation, rather than memorizing the factor of two, is what lets you reason about more elaborate wideband topologies later.

A Fully Worked Numerical Example

Use two identical NMOS devices with $g_m = 2\ \text{mS}$ and $r_o = 50\ \text{k}\Omega$ (from the MOSFET model article, each biased at 1 mA). A single common-source stage with an ideal load would have intrinsic gain

The cascode output resistance is

and, with a matching high-impedance load, the cascode gain is

The output resistance leapt from 50 kΩ to 5 MΩ — a factor of 100 — and the intrinsic gain from 100 to 10,000, a 40 dB improvement, all at the same 1 mA bias current. Meanwhile, if $C_{gd1} = 5\ \text{fF}$, the Miller capacitance in a plain CS stage of gain 100 would be $5\ \text{fF} \times 101 \approx 505\ \text{fF}$, whereas in the cascode it is only about $2 \times 5\ \text{fF} = 10\ \text{fF}$ — a 50-fold reduction in the dominant input capacitance.

Single Stage vs. Cascode

Common Mistakes

• Expecting high gain into a small resistive load. The $(g_m r_o)^2$ gain only materializes with a load comparable to $R_{out}$. A 10 kΩ resistor kills the benefit; you need an active (cascode current-source) load.
• Applying $g_m r_o^2$ to a BJT without limit. The finite base resistance $r_\pi$ caps the bipolar cascode output resistance at about $\beta r_o$, not $g_m r_o^2$.
• Forgetting the body effect on the top device. In a MOS cascode the source of $M_2$ is not at the bulk potential, so $g_{mb}$ appears and slightly raises the impedance-boost factor to $(g_{m2}+g_{mb2})r_{o2}$.
• Assuming the cascode removes all bandwidth limits. It tames the input Miller pole, but the output node now sees a very high resistance, creating a low-frequency output pole. The cascode shifts where the bandwidth limit lives; it does not abolish it.
• Dropping $r_o$ anywhere. The entire cascode advantage is an $r_o$ effect. Setting $r_o \to \infty$ makes the analysis meaningless.

To experiment, build a two-transistor cascode in the CircuitMath editor and inspect the generated small-signal equations, or revisit the single-stage common-source amplifier to see exactly what the cascode improves upon.