Common Source Amplifier: Analysis and Design

The Common-Source Amplifier

The common-source (CS) stage is to MOSFET design what the common-emitter stage is to bipolar design: the fundamental inverting voltage amplifier from which nearly every CMOS gain block is built. A signal enters the gate, the drain current it modulates flows through a drain resistor or active load, and an amplified, inverted copy appears at the drain. Because the gate draws no DC current, the CS stage offers something the common-emitter stage cannot match: a nearly infinite input resistance. This tutorial derives the CS gain and impedances from the small-signal model, adds source degeneration, and grounds everything in a worked numerical example. If the parameters below are unfamiliar, review the MOSFET small-signal model first.

Building the Small-Signal Equivalent

Take a CS stage with the source at AC ground, a drain resistor $R_D$ to the supply, and the output taken at the drain. Kill the DC supply, short the coupling capacitors at midband, and substitute the MOSFET model: a transconductance source $g_m v_{gs}$ from drain to source with output resistance $r_o$ in parallel, and an open circuit at the gate. With the source grounded, the controlling voltage is the full input, $v_{gs} = v_i$.

Writing KCL at the drain, the controlled current $g_m v_{gs}$ flows out of the drain node and develops a voltage across the parallel combination of $R_D$ and $r_o$. Because the current is pulled out of the node, the output moves opposite to the input.

Voltage Gain and Impedances

The unloaded midband gain is

identical in form to the common-emitter result, with $R_D$ playing the role of $R_C$. Neglecting channel-length modulation gives the familiar $A_v \approx -g_m R_D$. The input and output resistances are

The infinite input resistance is the headline advantage of the CS stage. It draws no current from the source driving it, so it can be cascaded without the input-loading penalty that burdens the common-emitter stage. The price is lower transconductance per unit current, hence lower gain at a given bias.

Source Degeneration

Add an unbypassed source resistor $R_S$. As in the bipolar case, this is series feedback that stabilizes the gain against device variation. Neglecting $r_o$:

When $g_m R_S \gg 1$ this approaches $A_v \approx -R_D / R_S$, a gain fixed by a resistor ratio and immune to shifts in $g_m$. Because the gate still draws no current, the input resistance remains infinite — unlike the bipolar stage, degeneration here does not raise an already-finite input resistance; it simply leaves it infinite while trading gain for linearity and bandwidth. (If the source and body are not tied, the body-effect term $g_{mb}$ adds to $g_m$ in the degeneration denominator.)

Why the CS Stage Behaves the Way It Does

It is worth pausing to understand the physical story behind these equations, because the algebra alone can obscure what is really happening. The gate voltage controls the channel charge, which sets the drain current; the drain resistor then converts that current variation back into a voltage. The stage is therefore a transconductance amplifier wrapped by a current-to-voltage conversion, and that two-step character is exactly why the gain is the product $g_m$ times a resistance. Anything that weakens the link between input voltage and channel current — source degeneration, the body effect, a low $g_m$ from a small bias current — reduces the gain. Anything that raises the impedance at the drain, such as an active load, increases it. Holding this picture in mind lets you predict the direction of any design change before you reach for a calculator.

The CS stage also sets the template for the source follower and the common-gate stage, which are simply the same transistor with a different terminal grounded. In the source follower the output is taken at the source and the gain is close to unity but with very low output resistance; in the common-gate stage the input enters the source and the stage is non-inverting with low input resistance. All three share the same device parameters; only the terminal assignments differ. Recognizing that a single small-signal model generates this whole family of stages is one of the genuine payoffs of learning the model carefully rather than memorizing gain formulas in isolation.

Frequency response deserves a brief mention as well. At midband the capacitors are treated as shorts (coupling) or opens (device capacitances), and the gain is flat. At low frequency the coupling and bypass capacitors roll the gain off; at high frequency the gate-drain capacitance, multiplied by the Miller effect, dominates and creates the upper cutoff. Because the CS gain is large and inverting, that Miller multiplication is severe — which is precisely the problem the cascode topology was invented to solve, and the reason the two stages are so often studied back to back.

A Fully Worked Numerical Example

Use the device from the MOSFET model article: $k = 2\ \text{mA/V}^2$, $I_D = 1\ \text{mA}$, $\lambda = 0.02\ \text{V}^{-1}$, giving $V_{ov} = 1\ \text{V}$, $g_m = 2\ \text{mS}$, and $r_o = 50\ \text{k}\Omega$. Choose $R_D = 10\ \text{k}\Omega$. The undegenerated gain, keeping channel-length modulation, is

Neglecting $r_o$ would give $-g_m R_D = -(2\ \text{mS})(10\ \text{k}\Omega) = -20$, a 17% overestimate — larger than the bipolar example because $r_o = 50\ \text{k}\Omega$ is only five times $R_D$, so here keeping $r_o$ genuinely matters. Now add $R_S = 500\ \Omega$, so $g_m R_S = (2\ \text{mS})(500\ \Omega) = 1$:

The gain halves to −10, but it is now far less sensitive to the exact value of $g_m$ — double $g_m$ and the undegenerated gain would double, whereas the degenerated gain moves only from −10 toward the −20 ceiling set by $-R_D/R_S$. That insensitivity is exactly why degeneration is used in precision and wideband stages.

Common-Source vs. Common-Emitter

Common Mistakes

• Assuming a finite input resistance. The MOSFET gate is open at DC; $R_{in}$ is set only by the bias network, not by the device. There is no $r_\pi$.
• Neglecting $r_o$ when it is comparable to $R_D$. MOSFET $r_o$ is often far smaller than BJT $r_o$, so the $R_D \parallel r_o$ correction is frequently significant.
• Dropping the minus sign. The CS stage inverts. A positive gain is wrong.
• Forgetting the body effect in degeneration. If the source is not tied to the bulk, the effective transconductance in the denominator is $g_m + g_{mb}$.
• Confusing a bypassed and unbypassed $R_S$. A bypass capacitor across $R_S$ restores the full $-g_m R_D$ gain at midband; the degeneration formula applies only when $R_S$ is unbypassed.

Next, see how placing a second transistor on top of the CS device tames the output resistance and the Miller effect in the cascode tutorial, or build the stage in the CircuitMath editor to generate its equations automatically.