Common Emitter Amplifier: Gain, Input and Output Impedance

VCCRCvinvout
Common-emitter amplifier (DC bias network simplified).

The Common-Emitter Amplifier

The common-emitter (CE) stage is the workhorse of bipolar amplifier design and the first amplifier topology every analog course studies in depth. It delivers high voltage gain, a moderate input resistance set by rπr_\pi, and an output that is inverted with respect to the input. Understanding the CE stage cold is the prerequisite for everything that follows — differential pairs, cascodes, gain stages inside op-amps. In this tutorial we take the stage apart with the hybrid-pi model, derive the gain and impedances from KVL and KCL, add emitter degeneration to see how it trades gain for linearity, and finish with a complete numerical example. If you have not yet met the device model, read the BJT small-signal model first, since we use gmg_m, rπr_\pi, and ror_o freely below.

Setting Up the Small-Signal Circuit

Start with a CE stage: input viv_i applied through a coupling capacitor to the base, emitter at AC ground, collector tied to +VCC+V_{CC} through a collector resistor RCR_C, output vov_o taken at the collector. To analyze the signal behavior we kill the DC supply (short VCCV_{CC} to ground), treat the coupling and bypass capacitors as shorts at midband, and replace the transistor with its hybrid-pi equivalent: rπr_\pi from base to emitter, the current source gmvbeg_m v_{be} from collector to emitter, and ror_o in parallel.

With the emitter at AC ground, the controlling voltage is simply the input, vbe=viv_{be} = v_i. KCL at the collector node sums the current pulled by the transconductance source, the current through ror_o, and the current through RCR_C. Because the dependent source draws current from the collector into the device, the output swings opposite to the input — this is the origin of the minus sign in the gain.

Voltage Gain Without Degeneration

The output voltage equals the controlled current times the total resistance seen at the collector, which is RCR_C in parallel with ror_o. Carrying the sign through:

Av=vovi=gm(RCro)A_v = \frac{v_o}{v_i} = -g_m (R_C \parallel r_o)

If you neglect the Early effect (let ror_o \to \infty), this collapses to the textbook approximation AvgmRCA_v \approx -g_m R_C. The negative sign is not optional bookkeeping — it tells you the CE stage is inverting, a fact that matters when you close a feedback loop around it.

Input and Output Resistance

Looking into the base, an undegenerated CE stage presents rπr_\pi (in parallel with any bias resistors). Looking back into the collector, with the input source set to zero so vbe=0v_{be} = 0 and the dependent source is off, you see only ror_o; including the external load the output resistance of the stage is

Rin=rπ,Rout=roRCRCR_{in} = r_\pi, \qquad R_{out} = r_o \parallel R_C \approx R_C

The moderate input resistance is the CE stage's main weakness — it loads the previous stage. The high (inverting) gain is its main strength.

Emitter Degeneration

Insert an unbypassed resistor RER_E in the emitter leg. Now the emitter is no longer at AC ground; part of the input is dropped across RER_E, providing series-series local feedback. Neglecting ror_o, the gain becomes

Av=gmRC1+gmRE=RC1gm+REA_v = -\frac{g_m R_C}{1 + g_m R_E} = -\frac{R_C}{\tfrac{1}{g_m} + R_E}

When gmRE1g_m R_E \gg 1, this simplifies to the remarkably robust result AvRC/REA_v \approx -R_C / R_E, a gain set entirely by a ratio of resistors and independent of the bias-dependent gmg_m. You pay for this stability with reduced gain, but you gain wider bandwidth, lower distortion, and a much higher input resistance:

Rin=rπ+(β+1)RER_{in} = r_\pi + (\beta + 1) R_E

The term (β+1)RE(\beta + 1) R_E is the emitter resistor reflected into the base — the same current-gain factor that distinguishes rπr_\pi from rer_e.

The Physical Intuition Behind the Gain

Before plugging in numbers, it helps to see why the gain takes the form it does. A small change in vbev_{be} produces a proportionally larger change in collector current through gmg_m; that current then flows through the collector resistance and is converted into an output voltage. The amplifier is, at heart, a transconductance followed by a current-to-voltage conversion. This is why the gain is a product of gmg_m and a resistance rather than a simple resistor ratio — and why a transistor biased at higher current (larger gmg_m) gives more gain into the same load. The inversion arises because increasing the input pulls more current through the collector, dragging the collector voltage down toward ground.

Emitter degeneration changes this story in an instructive way. By leaving a resistor in the emitter, the signal current must develop a voltage across RER_E that subtracts from the input, so only a fraction of viv_i actually appears across the base-emitter junction. This is negative feedback in its most direct form: the stage opposes its own input. The benefit is that the gain becomes nearly independent of the transistor's exact gmg_m, which drifts with temperature and varies from device to device. Trading raw gain for predictability is one of the most common and important bargains in all of analog design, and the CE stage is where most engineers first encounter it.

It is also worth noting how the common-emitter stage fits into larger systems. Its inverting, high-gain behavior makes it the natural gain element inside operational-amplifier signal paths and the active device in many feedback loops. Its moderate input resistance, set by rπr_\pi, means it is usually preceded by a buffer or driven from a low-impedance source so that the loading does not erode the signal. Recognizing these system-level consequences of the small-signal parameters — not just memorizing the gain formula — is what turns the CE stage from a homework exercise into a design tool.

A Fully Worked Numerical Example

Bias an NPN at IC=1 mAI_C = 1\ \text{mA} with β=100\beta = 100, VA=100 VV_A = 100\ \text{V},VT=25 mVV_T = 25\ \text{mV}, and RC=5 kΩR_C = 5\ \text{k}\Omega. From the device model:

gm=1 mA25 mV=40 mS,rπ=1000.04=2.5 kΩ,ro=1000.001=100 kΩg_m = \frac{1\ \text{mA}}{25\ \text{mV}} = 40\ \text{mS}, \quad r_\pi = \frac{100}{0.04} = 2.5\ \text{k}\Omega, \quad r_o = \frac{100}{0.001} = 100\ \text{k}\Omega

The undegenerated gain, keeping the Early effect, is

Av=gm(RCro)=(0.04)(51005+100kΩ)=(0.04)(4.76 kΩ)=190A_v = -g_m (R_C \parallel r_o) = -(0.04)\left(\frac{5 \cdot 100}{5 + 100}\,\text{k}\Omega\right) = -(0.04)(4.76\ \text{k}\Omega) = -190

Dropping ror_o would give AvgmRC=(0.04)(5000)=200A_v \approx -g_m R_C = -(0.04)(5000) = -200 — only a 5% error here, so the approximation is acceptable for this small RCR_C. Now add an unbypassed RE=250 ΩR_E = 250\ \Omega. Since gmRE=(0.04)(250)=10g_m R_E = (0.04)(250) = 10:

Av=gmRC1+gmRE=2001+10=18.2A_v = -\frac{g_m R_C}{1 + g_m R_E} = -\frac{200}{1 + 10} = -18.2

Degeneration cut the gain from −200 to about −18 (close to the resistor ratio RC/RE=20-R_C/R_E = -20), but the input resistance jumped from rπ=2.5 kΩr_\pi = 2.5\ \text{k}\Omega to rπ+(β+1)RE=2.5k+(101)(250)=27.8 kΩr_\pi + (\beta+1)R_E = 2.5\,\text{k} + (101)(250) = 27.8\ \text{k}\Omega, more than ten times larger. That is the degeneration bargain in one line of arithmetic.

Summary: CE Stage With and Without Degeneration

QuantityUndegeneratedWith R_E (unbypassed)
Voltage gaingm(RCro)-g_m (R_C \parallel r_o)gmRC/(1+gmRE)-g_m R_C / (1 + g_m R_E)
Input resistancerπr_\pirπ+(β+1)REr_\pi + (\beta+1)R_E
Output resistanceroRCr_o \parallel R_CHigher (degeneration boosts ror_o)
Example gain (above)−190−18.2

Common Mistakes

  • Losing the minus sign. The CE stage is inverting. Reporting a positive gain is a sign error that will haunt any feedback analysis.
  • Forgetting that a bypassed RER_E is a short. If a large bypass capacitor sits across RER_E, the emitter is at AC ground and the gain is the full gmRC-g_m R_C — the degeneration formula does not apply at midband.
  • Using rer_e in the input-resistance formula. Input resistance into the base uses rπr_\pi and reflects RER_E by (β+1)(\beta+1), not by 1.
  • Ignoring ror_o with an active load. With a current-source load comparable to ror_o, you must keep it or the gain blows up to nonsense.
  • Mixing DC and AC. Solve the DC bias for ICI_C first, then build the small-signal circuit with sources killed. Do not carry DC supply voltages into the gain equations.

Once the CE stage is clear, compare it with its FET cousin in the common-source amplifier tutorial, then see how stacking two transistors boosts output resistance in the cascode analysis. You can also sketch the stage in the CircuitMath editor and have the KVL/KCL equations generated for you.

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